系统 Fpga 与 Cpu Latency

Systems Fpga Vs Cpu Latency

专题: Systems & Architecture / 系统与架构
难度: L2
来源: MyntBit

个人笔记

题目详情

高频交易公司优先最小化订单执行延迟。设计交易系统时，需要在 CPU 架构和 FPGA 架构之间选择订单处理方案。

考虑因素：确定性延迟（处理时间一致性对交易至关重要）；操作系统开销（CPU 需要操作系统引入不可预测的中断和调度延迟）；可编程性（FPGA 开发周期更长但提供硬件级并行）；成本（FPGA 单位成本更高但功耗更低）。

任务：在以下场景下比较 CPU 和 FPGA 方案：(1) 延迟敏感的订单路由，(2) 大规模并行行情解析。给出每种场景的最优选择和理由。

英文原题

High-frequency trading (HFT) firms prioritize minimizing latency in order execution. You are designing a trading system and must choose between using a CPU-based architecture or an FPGA-based architecture for order processing.
Consider the following factors:
Deterministic Latency: The consistency of processing time is crucial.
Operating System Overhead: CPUs require operating systems that introduce jitter and context switching.
Parallelism: The ability to execute tasks concurrently.

解析

问题分析

解法

根据题目要求实现相应功能。核心逻辑需要：

// 核心数据结构和方法——根据题目 API 约定实现
// 1. 确定状态表示——选择支持所需操作的数据结构
// 2. 实现核心算法——确保 O(·) 时间复杂度和正确性
// 3. 处理边界条件——空输入、极值参数、并发访问

验证

用具体输入验证：构造已知输入的测试用例，确认输出匹配预期结果。

复杂度与边界

时间复杂度：取决于选用的算法
空间复杂度：取决于数据规模
关键边界条件：空输入、极值参数、并发场景下的正确性保证

英文解析

Analysis

HFT firms prioritize minimizing latency in order execution. You must choose between a CPU-based or FPGA-based architecture for order processing. FPGA provides deterministic latency because all operations execute in fixed clock cycles with no scheduling jitter, cache misses, or context switches. CPU provides lower average latency but higher variance due to cache effects, branch prediction, and OS scheduling. FPGA latency is deterministic at ~1us with zero jitter; CPU average is ~2us but 99th percentile can reach 10-50us due to cache misses and context switches.

Solution

struct LatencyProfile { double avg_us; double p99_us; double max_us; bool deterministic; };;
LatencyProfile fpga_profile = {1.0, 1.0, 1.0, true};   // Deterministic
LatencyProfile cpu_profile  = {2.0, 10.0, 50.0, false}; // Variable
// Decision: FPGA for latency-critical path (order matching, risk checks)
//           CPU for strategy logic (flexibility, easier development)

Complexity & Edge Cases

Time complexity: FPGA O(fixed_cycles), CPU O(variable with cache effects)
Space complexity: FPGA limited by gate count, CPU limited by RAM
Edge cases: (1) FPGA development is expensive and slow (2) CPU can run complex strategies that FPGA cannot (3) Hybrid: FPGA for fast path, CPU for slow path

Verification

Benchmark FPGA vs CPU for order processing. Measure average and tail latency. FPGA should show zero jitter (all samples at same latency). CPU should show significant tail latency at 99th percentile.

Key Considerations

FPGA is chosen for the ultra-low-latency fast path (packet parsing, order matching, risk limit checks) where deterministic latency is paramount. CPU handles strategy logic, logging, and monitoring where flexibility matters more than nanosecond optimization. The hybrid architecture (FPGA fast path + CPU slow path) is the industry standard - FPGA processes market data and generates orders in <1us, while CPU runs the strategy that decides WHAT to trade.